Electronic Design

Implement Abstraction By Encapsulation In SystemC

High-level design (HLD) represents a hardware design at a more abstract level than register transfer level (RTL). A high-level synthesis (HLS) tool then can be used to produce the RTL necessary to ...
Design-Reuse

SystemC library supporting OVM compliant verification methodology

This paper describes the SystemC library that support Open Verification Methodology as defined by Mentor Graphics and Cadence with their SystemVerilog–based approach. Application of the library in ...
EDN

The war is over: C++ and SystemC coexist in a single flow

Since its debut in 2004, the current generation of high-level synthesis (HLS) tools has made tremendous progress in terms of both quality of results (QoR) and wider applicability. The success of this ...
Design-Reuse

Implementation of a SystemC Assertion Library

Implementing advanced temporal assertions in SystemC is an error prone process due to the limited assertion capabilities of the class library. Current approaches ...
EDN

SystemC fitted for verification duties

SAN JOSE, Calif. — In a push to establish a new design verification standard, the Open SystemC Initiative last week announced the SystemC Verification standard, based on Cadence Design Systems Inc.'s ...