The computing industry has reached a significant milestone with the ratification of the 1.0 RISC-V Vector Specification. This development marks the beginning of a new era in computing efficiency, as ...
SANTA CLARA, Calif.--(BUSINESS WIRE)--SiFive, Inc., the gold standard for RISC-V computing, today announced that the company has partnered with Kinara to create a USB-based enablement board that ...
The 2024 RISC-V Summit North America marked a significant milestone for the RISC-V community with the ratification of the RVA23 Profile. This event signifies a major step forward in the evolution of ...
The RISC-V Summit North America, held on 22-23 October 2025 in Santa Clara, California, showcased the latest CPU cores featuring new vector processors, high-speed interfaces, and peripheral subsystems ...
Forbes contributors publish independent expert analyses and insights. Marco Chiappetta is a technologist who covers semiconductors and AI. SiFive just announced an array of new additions to its ...
RISC-V, the open-standard Instruction Set Architecture (ISA) conceived by UC Berkeley developers in 2010, is going from strength to strength. The RISC in RISC-V stands for Reduced Instruction Set ...
RISC-V cores are beginning to show up in heterogeneous SoCs and packages, shifting from one-off standalone designs toward mainstream applications where they are used for everything from accelerators ...
Quintauris has announced a technical partnership with Vector to integrate the MICROSAR Classic software stack into its RT-EUROPA real-time automotive platform, aiming to advance development of ...
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