FPGA-based prototyping solutions provider S2C has teamed up with RISC-V processor IP supplier Andes Technology to enhance prototyping capabilities for system-on-chip (SoC) designs. This collaboration ...
The PolarFire SoC Discovery Kit from Microchip makes RISC-V and FPGA design accessible to a wider range of embedded engineers. This low-cost development platform allows students, beginners, and ...
A longtime supporter of the RISC-V (pronounced RISC Five) instruction set architecture (ISA), Microsemi provides tools and RISC-V soft cores for its various FPGA lines, including the recently unveiled ...
Microchip Technology has launched what it says is the industry’s first RISC-V based system-on-chip (SoC) field programmable gate array (FPGA) development kit, available for under $500. The rising ...
Look upon this conference badge and kiss your free time goodbye. The 2019 Hackaday Superconference badge is an ECP5 FPGA running a RISC-V core in a Game Boy form factor complete with cartridge slot ...
Microchip’s PolarFire® SoC FPGA Icicle Kit enables the broad RISC-V-based Mi-V ecosystem for the industry’s lowest-power FPGA CHANDLER, Ariz., Sept. 16, 2020 (GLOBE NEWSWIRE) -- The rising adoption of ...
How a cool FPGA needs so little power. The importance of a smaller RISC-V SoC FPGA. What the PolarFire SoC means to RISC-V developers. Why security and reliability are key to PolarFire’s success. Very ...
BERKELEY, Calif. & SANTA CLARA, Calif.--(BUSINESS WIRE)--Today at the RISC-V Summit, the RISC-V Foundation, a non-profit corporation controlled by its members to drive the adoption and implementation ...
CHANDLER, Ariz., Feb. 15, 2024 (GLOBE NEWSWIRE) -- The embedded industry is seeing an increased demand for open-source RISC-V®-based processor architectures, but there are still limited options when ...
With the PolarFire SoC Discovery Kit, Microchip makes RISC-V and FPGA hardware available to engineers working at all levels. The RISC-V architecture is never far from the news. However, away from the ...
Efinix has announced its Topaz family of RISC-V-based SoC FPGAs designed for high-volume and mass-market applications. The new family aims to provide a balance of performance and cost efficiency for a ...
A technical paper titled “Enabling HW-based Task Scheduling in Large Multicore Architectures” was published by researchers at Barcelona Supercomputing Center, University of Campinas, University of Sao ...