For high-speed signal sampling and processing applications that need an array of synchronized analog-to-digital converters (ADCs), the ability to de-skew and match latency variation across the ...
The need for deterministic latency in converter-based applications. Three subclasses were introduced in JESD2054B to deal with deterministic latency. Implementation methods for subclasses 0, 1, and 2.
Some results have been hidden because they may be inaccessible to you
Show inaccessible results